Intel’s Arrow Lake-S Core Ultra 200 Series desktop processors have seemingly leaked. Not only that, but the source have also included a specific launch date for the lineup: 10 October this year.
According to the list of Core Ultra 200 CPUs posted by South Korean leakster harukaze5719, Intel will be launching no less than 14 SKUs in the lineup, including K and KF variants. The top of the line SKU for it will be the Core Ultra (CU) 9 285K, which will house eight Lion Cove P-Cores and 16 Skymont E-Cores, bringing the total number of cores-on-die to 24 cores. Further, it will have a TVB boost of 5.7GHz for up to two P-Cores.
ARL-S lineup. According to Benchlife, ARL-S will be released on October 10th.https://t.co/Nyo7gw5pmJ pic.twitter.com/JpxH5ZohG4
— 포시포시 (@harukaze5719) August 18, 2024
One point to note is that there are three variants of the same processor, with the 285T being the “lowest tier” and presumably made for energy efficiency, as it has a 35W TDP. Not only that, the base clocks for the P-Cores and E-Cores are 1.4GHz and 1.2GHz respectively, but can seemingly still turbo up to 4.7GHz and 4.5GHz, while TVB would bring it up to 5.4GHz.
In the same breath of this Core Ultra 200 lineup, it appears Intel is extending the generous 125W TDP to non-CU 9 SKUs, including the CU 7 and, surprisingly, two CU 5 SKUs — specifically, the 245K and 245KF. Another point to note that the list doesn’t mention any form of hyperthreading, confirming that the chipmaker is clearly doing away with it, just as it said it would do with its Lunar Lake mobile CPU platform.
Damn, I’m late.
Wanted to wait one more day for QS week. https://t.co/veLt4K0eb8 pic.twitter.com/YHbepLWkYY— Jaykihn (@jaykihn0) August 18, 2024
If the 10 October launch date is true, then it is highly likely that Intel will launch the K and KF variants first, while the non-K and T-Series SKUs of the Core Ultra 200 Series will be released later. So, best to just take treat this as a rumour and douse it with all the salt you have.
(Source: Harukaze5719 via X, Jaykihn via X)
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